1. Technical Field
Various embodiments generally relate to a semiconductor apparatus, and more particularly, to a semiconductor system including a pad and a bump having a metal layer.
2. Related Art
In order to improve the degree of integration within a semiconductor apparatus, a 3-dimensional (3D) semiconductor apparatus may be used. Integration within the 3D semiconductor apparatus may be improved by stacking and packaging a plurality of chips in a single package. A 3D semiconductor apparatus may have two or more vertically stacked chips and to help achieve the highest degree of integration within the limited space a semiconductor apparatus provides.
There are various ways to implement a 3D semiconductor apparatus. One of these ways are to stack a plurality of chips having the same structure and then couple the stacked chips to each other with a wire such as a metal line. This may allow the plurality of chips to act as a single semiconductor apparatus.
Another way to couple the stacked chips would be to use a, Through Silicon Via (TSV) scheme to pass through the stacked chips with a via. Using these TSVs may electrically couple all of the stacked chips. A TSV-implemented semiconductor apparatus uses TSVs to vertically pass through and couple the stacked chips. Using this scheme can efficiently reduce a package area of a semiconductor apparatus more than a scheme which implements the wire-implemented semiconductor apparatus. The wire-implemented semiconductor apparatus coupling the stacked chips through wires disposed in the border area of the chips.
Chips having the TSVs may be stacked through a metal pad and bump. The metal pad may be electrically coupled to the TSV and the bump may be stacked over the metal pad so that a signal input through the bump may be transferred to another semiconductor chip through the metal pad and the bump.